Damascene structures in semiconductor substrates are so-named because they consist of metal lines formed in narrow grooves, as illustrated by the structure shown at the bottom of FIG. 1. These metal lines may be of width W<0.15 μm and height H>0.5 μm, with an aspect ratio that may exceed 3:1 (ratio of height to width). The grooves may be formed within a dielectric layer that has a total thickness of 1 μm and a thickness between the bottom of the grooves and the bottom of the dielectric layer of T=0.5 μm.
Such damascene structures are typically formed in a multi-step process, of the type shown in FIG. 1. First, in step 110, photoresist layer 101 is formed on insulator layer 102 over substrate 103. Insulator 102 is a material such as silicon dioxide, and substrate 103 is silicon. In step 111, photoresist layer 101 is patterned, forming grooves 104a–f. The structure is then etched in step 112, forming grooves 105a–f in the insulator layer 102. Note that the grooves are less deep than the thickness of the insulator 102. The photoresist layer 101 is subsequently stripped. In step 113 the structure is coated with a barrier layer of a metal such as tantalum, followed by a seed layer of a metal such as copper, indicated as combined layers 105bs. The copper seed layer provides a conductive coating to allow electroplating of a thick copper layer onto the structure in step 114, that material being shown as layer 106. The seed layer may be 1000 Å thick on the surface, but only 100–200 Å thick on the walls of the grooves. Similarly, the tantalum layer may be 250 Å thick on the surface, but only 50 Å or less thick on the walls of the grooves. The tantalum layer prevents the copper from diffusing into the underlying layers; hence its name “barrier”, and also improves adhesion of the copper to insulator 102. In step 115 the electroplated layer 106 is polished away, leaving a fill of copper in the grooves.
The yield of this process depends on the thickness t of each sidewall of each groove. This is a parameter called sidewall coverage. If the sidewall coverage is too thin, then the coating may be discontinuous, or even non-existent. It then acts as a poor nucleating surface for the subsequent electrodeposition of subsequent thick layer 106, causing problems such as void formation. Specifically, voids may arise if the plating process does not begin properly on one of the sidewalls. For example, filling may not start at the bottom of a groove, resulting in a “bottom” void. As another example, if a groove fills from the side, but not the bottom, then a “center” void may occur.
Such voids Va–Vc (FIG. 1) act as breaks in the metal lines 107a–107c, either preventing current flow, or constricting current flow to the point where the line locally overheats and fails. If the coating is too thick, the top of the groove may close off, preventing adequate circulation of electrodeposition electrolyte, resulting in poor filling of the grooves which can also result in voids. This problem is further aggravated as the technology advances, and the grooves become deeper and narrower.
Voids in a semiconductor wafer can be generated in other ways as well. For example, voids in the metal line can be opened during chemical mechanical polishing (CMP). Also, voids may be created between a metal line and the underlying dielectric layer due to volume contraction that occurs after annealing. Furthermore, stress- and electromigration voids typically nucleate at intersections of metallization grain boundaries and the passivation/interconnect interface, and can form as a consequence of current flowing through the line, resulting in failure that may occur months after manufacture.
A prior art method for detection of voids is to electrically probe long runs of metal lines, often after electrical stress. However, this is not useful in production because it only finds the voids long after the process has been completed. In addition, it requires contact to the product wafer, and such long runs for void testing are not readily available on product, because they require considerable wafer area.
Voids may also be seen using FIB-SEM (Focused Ion Beam Scanning Electron Microscopy). A focused ion beam mills out a section of the line, and a scanning electron microscope is used to view the section. This method is slow and destructive, and views such a small area that it is only of use in cases of extremely high void density, or if the void location has been found by other means such as electrical testing.
An article at the website http://www.micromagazine.com/archive/00/01/prods.html published in January 2000 describes a “Wafer Inspection System” available from Schlumberger of San Jose, Calif., as follows “The Odyssey 3000 uses an E-beam-based voltage-contrast technology to identify yield-killing electrical defects that are difficult to detect using optical systems. Designed for use in sub-0.15-μm processes, the system detects electrical, submicron particle, and pattern defects. Metal stringers, poly gate shorts, and copper damascene voids are also detectable. Real-time off-line defect review with simultaneous inspection eliminates the need to buy off-line inspection tools. The system accommodates 300-mm wafers and features an advanced graphical user interface to simplify recipe setup. Die-to-die comparisons also enable users to carry out rapid defect review.”
However, such a system has limited application because it can only look at exposed layers. In many cases, lines with voids may be buried under a dielectric layer, and the formation of the dielectric layer may in fact have been the cause of the voids. The electron beam charges the dielectric, preventing its use in such cases. In addition, the voltage-contrast method is only of use in cases of extreme voiding, where the lines are almost completely broken. This is seldom the case; often the voids are smaller, but these small voids are critical to detect because they may grow into sources of failure due to factors described earlier, such as electromigration and stress.